Nov 26th, 2010 Successor project ZamiaCAD has become free software.
May 4th, 2004 The signs project has been ported to Java.
Oct 11th, 2002 Initial import to CVS. You can checkout signs sources now.
Oct 10th, 2002 Launch of signs's home at sourceforge.net
Aug 2002 Light! First lines of signs were coded.
Signs is currently not actively maintained (Dec 2011).
You can find the sources of this project as download and in the svn
repository. It might be helpful to you if you want to build something
similar to signs.
"Signs" stands for "Simple Gate Net Simulator".
The project goal is to provide a set of tools for gate-level logic synthesis, analysis and simulation, based on a subset of VHDL. This includes gnc, the gate net compiler which understands an easily synthesizable subset of VHDL (but includes behavioural VHDL constructs) and gns, the gate net simulator and analyzer which provides a graphical netlist viewer and an event-based gatelevel simulator. More tools may be added later, especially place+route tools to generate FPGA programming data are planned.
Signs is, at least for now, mainly aimed at teaching/educational purposes and not
yet suited for production circuit design.
Most development will is done the Java programming language.
©2011 by the signs project - last change: 22.12.2011