The Signs Project
About - Resources - Contact

News

Nov 26th, 2010 Successor project ZamiaCAD has become free software.

May 4th, 2004 The signs project has been ported to Java.

Oct 11th, 2002 Initial import to CVS. You can checkout signs sources now.

Oct 10th, 2002 Launch of signs's home at sourceforge.net

Aug 2002 Light! First lines of signs were coded.

About

Signs is currently not actively maintained (Dec 2011). You can find the sources of this project as download and in the svn repository. It might be helpful to you if you want to build something similar to signs.

"Signs" stands for "Simple Gate Net Simulator".

The project goal is to provide a set of tools for gate-level logic synthesis, analysis and simulation, based on a subset of VHDL. This includes gnc, the gate net compiler which understands an easily synthesizable subset of VHDL (but includes behavioural VHDL constructs) and gns, the gate net simulator and analyzer which provides a graphical netlist viewer and an event-based gatelevel simulator. More tools may be added later, especially place+route tools to generate FPGA programming data are planned.

Signs is, at least for now, mainly aimed at teaching/educational purposes and not yet suited for production circuit design. Most development will is done the Java programming language.

Resources

Related Projects: Information about VHDL:

Contact

Main developers:

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2011 by the signs project - last change:
Warning: date(): It is not safe to rely on the system's timezone settings. You are *required* to use the date.timezone setting or the date_default_timezone_set() function. In case you used any of those methods and you are still getting this warning, you most likely misspelled the timezone identifier. We selected the timezone 'UTC' for now, but please set date.timezone to select your timezone. in /home/project-web/signs/htdocs/tpl/footer.php on line 6
22.12.2011